1. Field of the Invention
The present invention relates to semiconductor technology. More particularly, the present invention relates to memory cell technology and to resistive random access memory cell technology. The present invention relates to low leakage resistive random access memory cells.
The contents of co-pending application Ser. No. 62/268,699, entitled LOW LEAKAGE RESISTIVE RANDOM ACCESS MEMORY CELLS AND PROCESSES FOR FABRICATING SAME; Ser. No. 62/401,875, entitled THREE-TRANSISTOR RESISTIVE RANDOM ACCESS MEMORY CELLS; and Ser. No. 62/402,927, entitled THREE-TRANSISTOR RESISTIVE RANDOM ACCESS MEMORY CELLS are expressly incorporated herein by reference in their entirety.
2. The Prior Art
Resistive random access memory (ReRAM) push-pull memory cells make an attractive configuration memory for advanced field-programmable gate array (FPGA) integrated circuits due to their small size and scalability. Examples of ReRAM memory devices and memory cells configured from those devices are disclosed in U.S. Pat. No. 8,415,650.
A ReRAM device is basically two metal plates, one of which serves as a metal ion source, separated by a solid electrolyte. The solid electrolyte has two states. In a first state (an “on” state), ions from the metal ion source have been forced into the electrolyte by placing a DC voltage having a first polarity across the ReRAM device and having a sufficient potential to drive metal ions from the ion-source plate into the electrolyte. In the first state, the ions form a conductive bridge through the solid electrolyte across which electrons can pass fairly easily. As the electrolyte becomes increasingly populated with metal ions, its resistivity, and hence the resistivity of the entire ReRAM device decreases. In a second state (an “off state), the electrolyte has been virtually depleted of ions by placing a DC voltage having a polarity opposite to that of the first potential and a potential sufficient to drive the metal ions from the electrolyte back into the ion-source plate across the ReRAM device. In the second state, absence of the ions makes it difficult for electrons to pass through the solid electrolyte. As the population of metal ions in the electrolyte decreases, its resistivity, and hence the resistivity of the entire ReRAM device increases. Amorphous silicon is a solid electrolyte and it is a leading candidate today for use in ReRAM devices.
ReRAM devices are often employed in a push-pull configuration to form a ReRAM memory cell as shown in FIG. 1. ReRAM memory cell 10 includes a first ReRAM device 12 in series with a second ReRAM device 14. In the ReRAM device symbols shown in FIG. 1, the wider (bottom) end of the ReRAM device is the end nearest its ion source. A voltage applied across the ReRAM device with its positive potential at the narrower (top) end of the ReRAM device will erase the device, i.e., set it to its “off” state, and a voltage applied across the ReRAM device with its positive potential at the wider (bottom) end of the ReRAM device will program the device, i.e., set it to its “on” state.
The ReRAM devices 12 and 14 are connected in series between a pair of complementary bitlines (BL) 16 (BL!) 18. Persons of ordinary skill in the art will appreciate that the value of the potentials applied to (BL) 16 and (BL!) 18 will be selected as a function of the particular feature size and other aspects of the technology employed. Typical operating voltages that are applied to (BL) 16 and (BL!) 18 are 1.5V and 0V, respectively.
In operation, one of ReRAM devices 12 and 14 will be set to its “on” state and the other will be set to its “off” state. Depending on which one of the ReRAM devices 12 and 14 is “on” and which one is “off” switch node 20 will either be pulled up to the voltage on BL 16 or pulled down to the voltage on BL! 18.
The gate of a switch transistor 22 is coupled to a switch node 20. The drain of the switch transistor 22 is connected to a first programmable node 24 and the source of the switch transistor is connected to a second programmable node 26. The first programmable node 24 can be connected to the second programmable node 26 by turning on the switch transistor 22.
If ReRAM device 12 is in its “on” state and ReRAM device 14 is in its “off” state, switch node 20 is pulled up to the voltage on BL 16, and switch transistor 22 will be turned on. If ReRAM device 12 is in its “off” state and ReRAM device 14 is in its “on” state, switch node 20 is pulled down to the voltage on BL! 18, and switch transistor 22 will be turned off. Persons of ordinary skill in the art will note that the entire potential between (BL) 16 and (BL!) 18 will exist across the one of ReRAM devices 12 and 14 that is in the “off” state.
A programming transistor 28 has a gate coupled to a word line (WL) 30. The drain of programming transistor 28 is connected to switch node 20 and its source is connected to a word line source (WLS) 32. In a typical application, ReRAM devices 12 and 14 are first erased (set to their “off” state) and then one of them is programmed (set to its “on” state) as described herein with reference to FIG. 5.
Referring now to FIG. 2, a cross sectional view of an illustrative semiconductor layout for a ReRAM cell 10 like that of FIG. 1 is shown. The ReRAM cell 10 is shown formed in a p-type semiconductor substrate 34, which may be a p-well structure as is known in the art. Shallow trench isolation (STI) regions 36 separate active regions for the switch transistor, the programming transistor and other adjacent structures. N-type doped region 38 forms the drain of the programming transistor and n-type region 40 forms its source. A contact 42 connects source 40 of the programming transistor to a first segment 44 of a first layer (M1) of metal interconnect forming WLS 32 described above. Polysilicon line 46 forms the gate of the programming transistor 28 and also acts as word line WL 30. Persons of ordinary skill in the art will appreciate that n-type region 40 can also serve as the source of a programming transistor for an adjacent ReRAM cell configured in a mirror cell arrangement with ReRAM memory cell 10 as is known in the art.
The switch transistor 22 is oriented orthogonally to the programming transistor 28 and polysilicon line 48 forms its gate. The source 26 and drain 24 regions of the switch transistor 22 are located in planes behind and in front of the plane of FIG. 2. Region 50 under the polysilicon line 48 is the channel of the switch transistor 22.
ReRAM device 12 is formed between a second segment 52 of the first layer (M1) of metal interconnect and a first segment 54 of a second layer (M2) of metal interconnect. An inter-metal contact 56 is shown connecting ReRAM device 12 to the first segment 54 of the second layer (M2) of metal interconnect. A second segment 58 of the second layer (M2) of metal interconnect serves as the bitline BL 16 and is connected to the second segment 52 of the first layer (M1) of metal interconnect by an inter-metal contact 60.
ReRAM device 14 is formed between a third segment 62 of the first layer (M1) of metal interconnect and a third segment 64 of the second layer (M2) of metal interconnect. The third segment 64 of the second layer (M2) of metal interconnect serves as the bitline BL! 18. An inter-metal contact 66 is shown connecting ReRAM device 14 to the third segment 64 of the second layer (M2) of metal interconnect.
An inter-metal contact 68 between the first segment 54 of the second layer (M2) of metal interconnect and the third segment 62 of the first layer (M1) of metal interconnect is used to make the connection between ReRAM device 12 and ReRAM device 14. Another pair of inter-metal contacts 70 and 72 and the third segment 62 of the first layer (M1) of metal interconnect are used to make the connection between the gate 48 of the switch transistor, the drain 38 of the programming transistor 28, and the common connection of the ReRAM devices 12 and 14.
ReRAM devices in the “off” state do not exhibit infinite resistance. ReRAM devices will therefore pass a leakage current in the “off” state if a voltage is impressed across them. For most normal memory applications, bits are only read when they are addressed. A transistor may be used to block any leakage current during times when the bit is not being read, and the leakage is therefore not overly problematic.
However, when using a ReRAM cell as a configuration memory for an FPGA, the cell statically drives the gate of a switch transistor to place the switch transistor in either its “on” or “off” state. In this application, the ReRAM cell is essentially always being read. Thus, the leakage current is always present across the ReRAM device that is in the “off” state, if a voltage is impressed thereacross, and is problematic.
Current investigations of the use of ReRAM memory cells as configuration memory in FPGA integrated circuits are academic in nature and ignore the cell leakage issue which presents a practical problem inhibiting the commercial application of this technology. Because the amount of “off” state leakage is an exponential function of the reverse, or “off” state, voltage across the ReRAM device it presents a significant obstacle to commercialization of ReRAM configuration memory in FPGA devices.